Ruben Otxoa
Senior researcher
I am a theoretical physicist developing the physical foundations for scalable, fault-tolerant quantum processors based on spin qubits. At Hitachi, I lead the theoretical roadmap connecting quantum error correction (QEC) with hardware design, from advanced QEC protocols to their implementation in realistic architectures. My research tackles key scalability bottlenecks in silicon through microscopic analytical modelling of spin-qubit shuttling and the exploitation of inherent noise to develop robust, hardware-aware QEC codes.
Researchgate: https://www.researchgate.net/profile/Ruben-M-Otxoa
